Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (the cells arranged in an array of rows and columns, each cell directly coupled to a bitline) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bitline and requires activating the other cells of the string for access). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
Because all the cells in an erase block of a Flash memory device must be erased all at once, one cannot directly rewrite a Flash memory cell without first engaging in a block erase operation. Erase block management (EBM) provides an abstraction layer for this to the host, allowing the Flash device to appear as a freely rewriteable device.
In non-volatile erase block based memory, such as Flash memory, because erasure is done on a block basis, if a data block/sector is updated the data block/sector cannot simply be written with the new data or, alternatively, directly erased and updated. A data update in non-volatile memory requires that the data be copied to a new location and the old data invalidated. For data integrity purposes the data is moved in the following manner: copying the updated data to the new location, writing the logical ID of the data block/sector to that new location, and finally invalidating the old data in the old data location. To invalidate a data block/sector, the control data section of each data block/sector typically contains a valid/invalid flag which changed from a “1” (an erased cell state) to a “0” (the programmed cell state) to invalidate the data block/sector.
One problem in setting this invalidation flag is that it can lead to program disturb in the surrounding rows and/or sectors of the memory array, affecting the stored charge of the floating gate memory cells of these rows and/or sectors and causing data reliability issues or even physically overwriting the stored data. This program disturb problem is particularly an issue with NAND architecture Flash memory arrays and devices due to their closely spaced array rows. This issue can also be a problem when multi-level memory cells (MLCs), which store multiple memory states in each cell, are utilized.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device and/or erase block management with improved data invalidation.